1. Field of the Invention
This invention relates to semiconductor devices, and more specifically to an overlay mark including segment regions and a pool region.
2. Description of Prior Art
A DRAM (Dynamic Random Access Memory), which is a typical semiconductor memory device, is manufactured in the following manner. First, on a semiconductor wafer, a world-line structure is formed on a semiconductor substrate. Subsequently, an intermediate insulating layer deposited on the semiconductor substrate is patterned via a photoresist to form a bit-line contact. To align the bit-line contact with the word-line structure, an overlay mark of the word-line structure is formed on the semiconductor substrate and that of the bit-line contact is formed by the photoresist. The overlay mark of the photoresist (hereinafter “upper level pattern”) is formed with the patterning of the photoresist for the bit-line contact. If the upper level pattern is misaligned to the overlay mark formed on the semiconductor substrate (hereinafter “an element set”) then the photoresist of the upper level pattern is reworked after stripped it. Before the intermediate insulating layer is etched via the photoresist, an alignment between the upper level and the lower level is performed to prevent misalignment of the word-line structure and bit-line contact.
An AIM (Advanced Imaging Metrology) mark (U.S. Pat. No. 8,330,281 B2), BiB (Bar in Bar) mark (Japanese Patent Application Laid Open No. 1998-125751), etc as the overlay mark are well-known. In the multi-patterning techniques (Japanese Patent Application Laid Open No. 2012-134378), such as SADP (Self Aligned Double Patterning), an extra, isolated groove (hereinafter “single groove”) is formed around a segment region including periodical grooves (trenches). The single groove is undesirable to deteriorate a measurement accuracy of the overlay mark in the alignment process.